Yu-Hui Huang
No.68, HankouSt,
Taitung, Taiwan 950, R.O.C.
Phone: +886-937601412
Email: dinlin@gmail.com
*EDUCATION
1999-2003 B.S. In Computer Science, National Tsing Hua University, HsinChu, Taiwan.
Overall GPA: 3.74/4.00 (144 credits)
Last 2 year GPA: 3.90/4.00 (62 credits)
2003-2005 M.S. In Computer Science, National Tsing Hua University, HsinChu, Taiwan.
Overall GPA: 4.00/4.00 (23 credits)
Master Thesis: “Switching Activity Driven Gate Sizing and Vth Assignment for Low Power Design” July 2005.
Advisor: Prof. TingTIng Hwang
*PUBLICATION
Yu-Hui Huang, Po-Yuan Chen and TingTing Hwang, "Switching Activity Driven Gate Sizing and Vth Assignment for Low Power Design," Proc. of ASP-DAC, Japan, Jan. 2006.
Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu, "Low-Power Techniques for Network Security Processors," Proc. of ASP-DAC, pp.355-360, China, 2005.
*WORKING EXPERIENCE
2001.9-2005.7 Homepage maintenances for National Tsing Hua University Center for Career Center and Division of Health Service.
2005.9-2007.8 Engineer, SpringSoft Inc. (Novas Taiwan).
2007.9-present Senior Engineer, SpringSoft Inc. (Novas Taiwan).
*AWARDS
3rd Prize(of 118 teams), Computer Aid Design Contest of Integrated Circuits, Ministry of Education, Taiwan, 2003. Topic: Hierarchical Overlapping Removing for Hierarchical layouts
*SKILLS
Programming Language: C/C++, Verilog, ASP, and Java.
Operating Systems: Ms-Windows, Linux, and Solaris.
Standard Cell-Based IC design Flow tool: Design Analyzer, Astro, and HSPICE.